ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Defocus-aware leakage estimation and control
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
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Leakage power became very predominant for nano scale devices i.e 90nm and 45nm. ITRS reports that leakage power dissipation may come to dominate total power consumption [1]. We propose a novel approach, which reduces leakage current while saving exact logic state. We designed Four bit Adder using traditional sleep transistors plus two additional transistors -- driven by a gate's already calculated output -- to save state during sleep mode. Dual Vth values can be applied in order to dramatically reduce sub threshold leakage current. In short, like the sleepy stack approach, our approach achieves leakage power reduction equivalent to the sleep and zigzag approaches but with the advantage of maintaining exact logic state (instead of destroying the logic state when sleep mode is entered). Based on experiments with a 4-bit adder circuit, our approach achieves up to 49% less delay and 49% less area than the sleepy stack approach. Unfortunately, our approach of using high Vt causes additional dynamic power consumption, approximately 15% more than the base case (no sleep transistors used at all). However, for applications spending the vast majority of time in sleep or standby mode while also requiring low area, high performance and maintenance of exact logic state, our approach provides a new weapon in a VLSI designer's arsenal.