Power-performance trade-offs in second level memory used by an ARM-like RISC architecture

Authors:
Kiran Puttaswamy;Lakshmi Narasimhan Chakrapani;Kyu-Won Choi;Yuvraj Singh Dhillon;Utku Diril;Pinar Korkmaz;Kyoung-Keun Lee;Jun Cheol Park;Abhijit Chatterjee;Peeter Ellervee;Vincent John Mooney, III;Krishna V. Palem;Weng-Fai Wong
Affiliations:
School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;Department of Computer Engineering, Tallinn Technical University;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Electrical and Computer Engineering, Georgia Institute of Technology;School of Computing, National University of Singapore
Venue:
Power aware computing
Year:
2002

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Abstract

Power consumption is an important dimension in microprocessor and digital system design. This is especially true in the embedded setting where microprocessors have to operate without the luxury of a large power supply or cooling structures. In this paper, we describe an infrastructure setup for the study of power-performance tradeoffs in microprocessor architecture and compiler optimizations. This infrastructure distinguishes itself from those already proposed in the literature in its use of power estimations based on synthesis of the architecture and the full integration of a well-established optimizing compiler framework. We present some preliminary results where we show how the circuit level and architectural techniques can be combined to save overall system power. In particular we reduce the clock frequency and supply voltage of level two memory accesses (circuit level technique) and compensate for the resulting increase in the completion time by implementing a non-blocking store buffer (architectural technique) resulting in up to 39 % less power and up to 28 % less energy on a set of candidate benchmarks.