A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies

Authors:
Amit Agarwal;Bipul C. Paul;Kaushik Roy
Affiliations:
Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN
Venue:
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Year:
2004

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Abstract

Process parameter variations are expected to be significantlyhigh in sub-50 nm technology regime, which can severely affectthe yield, unless very conservative design techniques areemployed. The parameter variations are random in nature andare expected to be more pronounced in minimum geometrytransistors commonly used in memories such as SRAM.Consequently, a large number of cells in a memory are expectedto be faulty due to variations in different process parameters. Inthis paper we analyze SRAM cell failure under process variationand propose a new fault tolerant cache architecture suitable forhigh performance applications. The faulty cells are dynamicallydetected and replaced by adaptively resizing the cache. Thegranularity of our resizing technique is low and hence, thetechnique can handle a large number of faults. This scheme istransparent to processor architecture and has negligible energyand area overhead. This scheme also does not affect the cacheaccess time and has minimum effect on processor performance.Experimental results on a 64K cache implemented using BPTM(Berkeley Predictive Technology Model) 45 nm technology showthat using our technique the effective yield can be increased to94% from its original 33%.