Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The Computer Engineering Handbook: Electrical Engineering Handbook
The Computer Engineering Handbook: Electrical Engineering Handbook
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust edge encoding technique for energy-efficient multi-cycle interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Insertion of time-borrowing (TB) flip-flops in multi-cycle repeater-based on-chip interconnects enables significant improvements in mean performance and energy by averaging systematic and random within-die (WID) delay variations across multiple interconnect segments. A statistically-based analytical model is derived to design a TB N-cycle interconnect with optimal delay variation tolerance. The model elucidates the dependency of the transparency window required to achieve data delay averaging on the delay variation mismatch between interconnect segments. Statistical circuit simulations and analyses in a 65nm process technology demonstrate that TB multi-cycle interconnects enable a 4-6% mean maximum clock frequency (FMAX) improvement and a corresponding 10% average energy savings over optimally designed multi-cycle interconnects with conventional master-slave flip-flops. The maximum mean FMAX benefit ranges from 4.0-7.5%, corresponding to approximately a bin-split shift in the FMAX distribution. For 1.41X larger WID delay variations, the maximum mean FMAX gain rises to 5-10%.