A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS

  • Authors:

  • Jaeyoung Kim;Kwen-Siong Chong;Joseph Sylvester Chang;Pinaki Mazumder

  • Affiliations:

  • University of Michigan, Ann Arbor, MI, USA;Nanyang Technological University, Singapore, Singapore;Nanyang Technological University, Singapore, Singapore;University of Michigan, Ann Arbor, MI, USA

  • Venue:
  • Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
  • Year:
  • 2013

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Abstract

Asynchronous approach for digital systems is a way to resolve increased timing uncertainty with technology scaling since timing issue is eliminated in asynchronous systems. This paper presents a sub-threshold operating asynchronous 8051 microcontroller (A8051) with a novel 16T SRAM cell for improved reliability in asynchronous systems. This A8051, adopting a 4-phase dual-rail protocol, can operate up to 250 mV. A8051 has 67.53 μs as a critical path delay with 91.6 nW power consumption at 250 mV, which is equivalent to 12.88 kHz in synchronous systems. At 1.0 V, the delay of a critical path of A8051 microcontroller is 5.74 ns, which is equivalent to 151.55 MHz, with 8.98 mW power consumption. The proposed 16T SRAM cell is applied in memory blocks. The 16T SRAM structure eliminates charge contentions between devices during read and write operations so that SRAM can be operated fully in static mode, bringing about improved write margin (WM). The WM of this 16T SRAM cell is 1.81 times greater than the conventional 6T SRAM cell and 1.58 times better than 8T SRAM cell. At 250 mV, the SNM of SRAM cell is 12.5 mV under process and mismatch variations. Write delay of the asynchronous SRAM block is 4.02 μs (equivalent to 248.5 kHz) with 5.44 pJ energy dissipation, while read delay is 12.61 μs (equivalent to 79.3 kHz) with 9.08 pJ energy dissipation.