Analysis and optimization of SRAM robustness for double patterning lithography

Authors:
Vivek Joshi;Kanak Agarwal;David Blaauw;Dennis Sylvester
Affiliations:
University of Michigan, Ann Arbor, MI;IBM Research Lab, Austin, TX;University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2010

Citing 2
Cited 0

Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

Double patterning lithography (DPL) is widely considered the only lithography solution for 32nm and several subsequent technology nodes. DPL decomposes and prints the critical layout shapes in two exposures, leading to mismatch between adjacent devices due to systematic offsets between the two exposures. This results in adjacent devices with different mean critical dimension (CD), and uncorrelated CD variation. Such a mismatch can increase functional failures in SRAM cells and degrade yield. This paper analyzes the impact of DPL on functional failures in SRAM bitcells, and proposes a DPL-aware SRAM sizing scheme to effectively mitigate yield losses. Experimental results based on 45nm industrial models and test chip measurements show that DPL can significantly impact SRAM cell robustness. Using the proposed DPL-aware sizing scheme, the SRAM cell failure probability can be reduced by up to 3.6X. Also, for iso-robustness, cells optimized by the proposed approach have 7.9% lower dynamic energy as compared to non-DPL aware sizing optimization.