Preventing timing errors on register writes: mechanisms of detections and recoveries

Authors:
Hidetsugu Irie;Ken Sugimoto;Masahiro Goshima;Shuich Sakai
Affiliations:
Japan Science and Technology Agency, Saitama, Japan;The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan
Venue:
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Year:
2007

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Abstract

To deal with the increasing varitations of the intra-chip transisters, one promising approach is to dynamically detect and recover the timing-errors with microarchitecutre. This will induce dependability and efficiency into microprocessors because it allows VLSI to operate at the optimum frequency and voltage while ensuring accuracy. A few approaches for dynamically detecting timing-errors have been proposed, but none of them have focused on register writes. In this paper, we propose a technique for detecting and recovering from timing errors during register writes. We introduce a verifying technique that uses additional buffer (called the write assurance buffer (WAB)) which is provided with a sufficient timing margin. The evaluation results reveal a performance degradation of 4.5% using an 8-entry WAB; this value becomes negligible when a 16-entry WAB is used.