Column-associative caches: a technique for reducing the miss rate of direct-mapped caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Review and future prospects of low-voltage RAM circuits
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 49th Annual Design Automation Conference
Performance and Power Solutions for Caches Using 8T SRAM Cells
MICROW '12 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops
Hi-index | 0.00 |
In this work, we propose a new multi-port 8T SRAM architecture suitable for DVFS enabled processors. With multi-way caches using 8T SRAM, write-back operations are required to support column selection. While conventional write-back schemes may not have the 1R/1W dual port advantage of 8T SRAM, our proposed local write-back scheme preserves both ports with only minimal limitations. Simulation results show significant IPC enhancements with the proposed cache. Implementation in 45nm technology demonstrates wide-range DVFS (from 120MHZ@0.48V to 710MHz@1V) for the proposed SRAM array.