Balanced allocations (extended abstract)
STOC '94 Proceedings of the twenty-sixth annual ACM symposium on Theory of computing
The power of two choices in randomized load balancing
The power of two choices in randomized load balancing
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
An O(v|v| c |E|) algoithm for finding maximum matching in general graphs
SFCS '80 Proceedings of the 21st Annual Symposium on Foundations of Computer Science
Microprocessors & Microsystems
Phase-change random access memory: a scalable technology
IBM Journal of Research and Development
Error Correction Codes for Non-Volatile Memories
Error Correction Codes for Non-Volatile Memories
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
Better I/O through byte-addressable, persistent memory
Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles
PACT '09 Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
Characterizing and mitigating the impact of process variations on phase change based memory systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Use ECP, not ECC, for hard failures in resistive memories
Proceedings of the 37th annual international symposium on Computer architecture
SAFER: Stuck-At-Fault Error Recovery for Memories
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Mnemosyne: lightweight persistent memory
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Page placement in hybrid memory systems
Proceedings of the international conference on Supercomputing
Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Wear rate leveling: lifetime enhancement of PRAM with endurance variation
Proceedings of the 48th Design Automation Conference
Energy-aware writes to non-volatile main memory
HotPower '11 Proceedings of the 4th Workshop on Power-Aware Computing and Systems
Energy-aware writes to non-volatile main memory
ACM SIGOPS Operating Systems Review
Preventing PCM banks from seizing too much power
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Pay-As-You-Go: low-overhead hard-error correction for phase change memories
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A resistive TCAM accelerator for data-intensive computing
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems
Proceedings of the 49th Annual Design Automation Conference
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 26th ACM international conference on Supercomputing
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches
Proceedings of the International Conference on Computer-Aided Design
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory
ACM Transactions on Architecture and Code Optimization (TACO)
Using managed runtime systems to tolerate holes in wearable memories
Proceedings of the 34th ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems
Phase-change memory: An architectural perspective
ACM Computing Surveys (CSUR)
Proceedings of the ACM International Conference on Computing Frontiers
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates
Proceedings of the 40th Annual International Symposium on Computer Architecture
Bit mapping for balanced PCM cell programming
Proceedings of the 40th Annual International Symposium on Computer Architecture
Zombie memory: extending memory lifetime by reviving dead blocks
Proceedings of the 40th Annual International Symposium on Computer Architecture
Optimizing video application design for phase-change RAM-based main memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A case study on the application of real phase-change RAM to main memory subsystem
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Approximate storage in solid-state memories
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memory
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
NVM duet: unified working memory and persistent store architecture
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer
ACM Transactions on Embedded Computing Systems (TECS)
A Unified Buffer Cache Architecture that Subsumes Journaling Functionality via Nonvolatile Memory
ACM Transactions on Storage (TOS)
Endurance-aware cache line management for non-volatile caches
ACM Transactions on Architecture and Code Optimization (TACO)
Unioning of the buffer cache and journaling layers with non-volatile memory
FAST'13 Proceedings of the 11th USENIX conference on File and Storage Technologies
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DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are a promising DRAM replacement. Unfortunately, PCM is write-limited, and current approaches to managing writes must de- commission pages of PCM when the first bit fails. This paper presents dynamically replicated memory (DRM), the first hardware and operating system interface designed for PCM that allows continued operation through graceful degradation when hard faults occur. DRM reuses memory pages that con- tain hard faults by dynamically forming pairs of complementary pages that act as a single page of storage. No changes are required to the processor cores, the cache hierarchy, or the operating sys- tem's page tables. By changing the memory controller, the TLBs, and the operating system to be DRM-aware, we can improve the lifetime of PCM by up to 40x over conventional error-detection techniques.