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SRAM supply voltage scaling: A reliability perspective
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Architecting phase change memory as a scalable dram alternative
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Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
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Use ECP, not ECC, for hard failures in resistive memories
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Proceedings of the 37th annual international symposium on Computer architecture
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Proceedings of the 37th annual international symposium on Computer architecture
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Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
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Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
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Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Improving write operations in MLC phase change memory
HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
Optimizing NAND flash-based SSDs via retention relaxation
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications
IEEE Transactions on Circuits and Systems for Video Technology
Neural Acceleration for General-Purpose Approximate Programs
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Zombie memory: extending memory lifetime by reviving dead blocks
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Proceedings of the 50th Annual Design Automation Conference
Error patterns in MLC NAND flash memory: measurement, characterization, and analysis
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Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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Memories today expose an all-or-nothing correctness model that incurs significant costs in performance, energy, area, and design complexity. But not all applications need high-precision storage for all of their data structures all of the time. This paper proposes mechanisms that enable applications to store data approximately and shows that doing so can improve the performance, lifetime, or density of solid-state memories. We propose two mechanisms. The first allows errors in multi-level cells by reducing the number of programming pulses used to write them. The second mechanism mitigates wear-out failures and extends memory endurance by mapping approximate data onto blocks that have exhausted their hardware error correction resources. Simulations show that reduced-precision writes in multi-level phase-change memory cells can be 1.7x faster on average and using failed blocks can improve array lifetime by 23% on average with quality loss under 10%.