A case study on the application of real phase-change RAM to main memory subsystem

Authors:
Suknam Kwon;Dongki Kim;Youngsik Kim;Sungjoo Yoo;Sunggu Lee
Affiliations:
Pohang University of Science and Technology (POSTECH);Pohang University of Science and Technology (POSTECH);Pohang University of Science and Technology (POSTECH);Pohang University of Science and Technology (POSTECH);Pohang University of Science and Technology (POSTECH)
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 16
Cited 0

Pin: building customized program analysis tools with dynamic instrumentation

Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Architecting phase change memory as a scalable dram alternative

Proceedings of the 36th annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology

Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology

Proceedings of the 36th annual international symposium on Computer architecture
PDRAM: a hybrid PRAM and DRAM main memory system

Proceedings of the 46th Annual Design Automation Conference
Characterizing and mitigating the impact of process variations on phase change based memory systems

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
On the lifetime of multilevel memories

ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 2
Dynamically replicated memory: building reliable systems from nanoscale resistive memories

Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Use ECP, not ECC, for hard failures in resistive memories

Proceedings of the 37th annual international symposium on Computer architecture
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping

Proceedings of the 37th annual international symposium on Computer architecture
SAFER: Stuck-At-Fault Error Recovery for Memories

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Onyx: a protoype phase change memory storage array

HotStorage'11 Proceedings of the 3rd USENIX conference on Hot topics in storage and file systems
Power management of hybrid DRAM/PRAM-based main memory

Proceedings of the 48th Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Phase-change RAM (PCM) has the advantages of better scaling and non-volatility compared with the DRAM which is expected to face its scaling limit in the near future. There have been many studies on applying the PCM to main memory in order to complement or replace the DRAM. One common limitation of these studies is that they are based on synthetic PCM models. In our study, we investigate the feasibility and issues of applying a real PCM to main memory. In this paper, we report our case study of characterizing the PCM and evaluating its usefulness in the main memory. Our results show that the PCM/DRAM hybrid main memory with a modest DRAM size can give comparable performance to that of the DRAM only main memory. However, the hybrid memory with small DRAMs or large footprint programs can suffer from performance degradation due to the long latency of both PCM writes and write preemption penalty, which requires architectural innovations for exploiting the full potential of PCM write performance.