Soft error mitigation in cache memories of embedded systems by means of a protected scheme
LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
| Hi-index | 0.00 |
The technology of SRAM-based devices is sensible to Single Event Upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. This paper presents a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results showthat between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device.