System-level interconnect architecture exploration for custom memory organizations
Proceedings of the 14th international symposium on Systems synthesis
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Data Mining: Practical Machine Learning Tools and Techniques, Second Edition (Morgan Kaufmann Series in Data Management Systems)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Rapid early-stage microarchitecture design using predictive models
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration for optimizing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.01 |
Specialising Systems-on-Chip (SOCs) for a particular application is an effective way of increasing the performance achievable for a given level of energy consumption. In fact, silicon manufacture costs are low enough that small, custom, entirely digital designs, up to and including multi-core microprocessor designs, can be manufactured cheaply in short manufacturing runs. Non-recurring engineering (Nre) costs are still prohibitive due to the high level of experience required from the design engineer and the vast size of the design space. This is even true when only pre-verified Commercial Off-the-Shelf (Cots) Intellectual Property (ip) blocks are used in the SoC design. In this paper we present a novel machine-learning based method of generating an application-specific SoC design and configuration. This approach is fully automated and can generate near-optimal application-specific SoC designs within hours rather than weeks and, hence, reduce both Nre costs and time-to-market significantly. Our methodology profiles key application characteristics using simulation of a small number of test systems and machine-learning based prediction to find likely optimal system designs for a given target application. We demonstrate the effectiveness of our automated design methodology using 82 workload applications, generate SoC designs with up to 10 cores and 8 memory banks, and show that our classifier averages up to 92% of the optimal design performance across our applications.