Optimal TDMA time slot and cycle length allocation for hard real-time systems

  • Authors:
  • Ernesto Wandeler;Lothar Thiele

  • Affiliations:
  • Swiss Federal Institute of Technology (ETH) Zurich, Switzerland;Swiss Federal Institute of Technology (ETH) Zurich, Switzerland

  • Venue:
  • ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
  • Year:
  • 2006

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Abstract

We present an analytic method to determine the provably smallest possible slot length that must be allocated in a TDMA resource, to serve an event-triggered hard real-time load with arbitrary deterministic timing behavior. Based on this method, we then present constructive methods to find all feasible as well as the optimal cycle length in a TDMA resource, and we show how to determine the minimum required band-width of a TDMA resource. We demonstrate the applicability and computational efficiency of the presented methods in a case study of a large distributed embedded system with a TDMA bus, where we will find the optimal parameter set for the TDMA bus.