An interface algebra for estimating worst-case traversal times in component networks

Authors:
Nikolay Stoimenov;Samarjit Chakraborty;Lothar Thiele
Affiliations:
Computer Engineering and Networks Laboratory, ETH Zurich, Switzerland;Institute for Real-Time Computer Systems, TU Munich, Germany;Computer Engineering and Networks Laboratory, ETH Zurich, Switzerland
Venue:
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
Year:
2010

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Abstract

Interface-based design relies on the idea that different components of a system may be developed independently and a system designer can connect them together only if their interfaces match, without knowing the details of their internals. In this paper we propose an interface algebra for analyzing networks of embedded systems components. The goal is to be able to compute worst-case traversal times and verify their compliance to provided deadlines in such component networks in an incremental manner, i.e., as and when new components are added or removed from the network. We lay the basic groundwork for this algebra and show its utility through an illustrative example.