A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
Optimized priority assignment for tasks and messages in distributed hard real-time systems
WPDRTS '95 Proceedings of the 3rd Workshop on Parallel and Distributed Real-Time Systems
A multiobjective optimization model for exploring multiprocessor mappings of process networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Rate analysis for streaming applications with on-chip buffer constraints
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Design Space Exploration and System Optimization with SymTA/S " Symbolic Timing Analysis for Systems
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal TDMA time slot and cycle length allocation for hard real-time systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Methods for power optimization in distributed embedded systems with real-time requirements
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Timing analysis of the FlexRay communication protocol
Real-Time Systems
Scheduling the FlexRay bus using optimization techniques
Proceedings of the 46th Annual Design Automation Conference
A new data flow analysis model for TDM
Proceedings of the tenth ACM international conference on Embedded software
Diversely enumerating system-level architectures
Proceedings of the Eleventh ACM International Conference on Embedded Software
Optimizing the implementation of real-time Simulink models onto distributed automotive architectures
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper we present arithmetic real-coded variation operators tailored for time slot and turn optimization on TDMA-scheduled resources with evolutionary algorithms. Our operators implement a heuristic strategy to converge towards the solution space and are able to escape local minima. Furthermore, we explicitly separate the variation of the admitted loads and the turn-length in order to give the designer increased control over the optimization process. Experimental results show that our variation operators have advantages over string-coded binary variation operators which are frequently used to solve continuous optimization problems.