Holistic schedulability analysis for distributed hard real-time systems
Microprocessing and Microprogramming - Parallel processing in embedded real-time systems
Modeling concurrent real-time processes using discrete events
Annals of Software Engineering
Embedded Software in Network Processors - Models and Algorithms
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Guaranteeing the quality of services in networks on chip
Networks on chip
QNoC Asynchronous Router with Dynamic Virtual Channel Allocation
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Computers and Electrical Engineering
Scalable parallel word search in multicore/multiprocessor systems
The Journal of Supercomputing
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Analyzing the delay characteristics of System-on-chip network on multi-core chip, establishing the signal flow model based on the signal flow structure and time measurement method, the network transfer mode based on the centralized leading node proposed the network routing algorithm and signal flow priority queuing transmission scheduling algorithm, and gave the signal flow delay time and the least upper bound calculation of router cache. At the same time, certified the scheduling algorithm can make sure the delay constraints, the result of algorithm meet the timely and determinism of real test.