Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Fundamentals of Computational Swarm Intelligence
Fundamentals of Computational Swarm Intelligence
Structured Computer Organization (5th Edition)
Structured Computer Organization (5th Edition)
Computer Organization and Design: The Hardware/Software Interface
Computer Organization and Design: The Hardware/Software Interface
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Multi-Processor System on Chip (MPSoC) offers a set of processors, embedded in one single chip. A parallel application can, then, be scheduled to each processor, in order to accelerate its execution. One problem in MPSoCs is the communication between processors, necessary to run the application. The shared memory provides the means to exchange data. In order to allow for non-blocking parallelism, we based the interconnection network in the crossbar topology. In this kind of interconnection, processors have full access to their own memory module simultaneously. On the other hand, processors can address the whole memory. One processor accesses the memory module of another processor only when it needs to retrieve data generated by the latter. This paper presents the specification and modeling of an interconnection network based on crossbar topology. The aim of this work is to investigate the performance characteristics of a parallel application running on this platform.