An QoS aware mapping of cores onto NoC architectures

Authors:
Huy-Nam Nguyen;Vu-Duc Ngo;Younghwan Bae;Hanjin Cho;Hae-Wook Choi
Affiliations:
System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University, Taejon, Korea;System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University, Taejon, Korea;Basic Research Laboratory, ETRI, Daejeon, Korea;Basic Research Laboratory, ETRI, Daejeon, Korea;System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University, Taejon, Korea
Venue:
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
Year:
2007

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Abstract

Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future SoC applications. The NoC, somewhat, resembles the parallel computer network. However, the NoC design highly requires the certain satisfaction of latency, power consumption, and area constraints. The latency of the network relates much to throughput and power consumption. Moreover, the IPs and the network are heterogeneous. Hence, a certain mapping of IPs onto a certain architecture produces a certain value of network latency as well as power consumption. The change of mapping scheme leads to a significant change of the values of these constraints. The fact that if we want to maximize the system's throughput, the network latency also increases and if we minimize the network latency, the trade off is that the throughput will decrease. In this paper, we present an mapping scheme that does compromise between throughput maximization and latency minimization. This sub-optimal mapping is found using the spanning tree searching algorithm. The experiment architecture using here is Mesh based topology. We use NS2 to simulate and calculate the system throughput and system power consumption is calculated using Orion model.