Minimization of crosstalk in high speed PCB

Authors:
D. Anish;G. Kranthi Kumar;Rohita Jagdale
Affiliations:
Department of Microelectronics and VLSI Design, International Institute of Information Technology, Hinjewadi, Pune, India;Department of Microelectronics and VLSI Design, International Institute of Information Technology, Hinjewadi, Pune, India;Department of Microelectronics and VLSI Design, International Institute of Information Technology, Hinjewadi, Pune, India
Venue:
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Year:
2010

Citing 1
Cited 1

High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices

High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices

A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC

Microelectronics Journal

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Abstract

Crosstalk is an important problem in high-speed printed circuit board design which is one of the signal integrity issues. A wildly used theoretical model based on microstrip theory is presented in this paper. On this basis, the origin and the factors affecting crosstalk are introduced. Cadence Allegro is used to analyze these factors.