A practical current sensing technique for IDDQ testing

Authors:
Jing-Jou Tang;Kuen-Jong Lee;Bin-Da Liu
Affiliations:
-;-;-
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1995

Citing 0
Cited 12

A Low-Loss Built-In Current Sensor

Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Design and Realization of a Built-In Current Sensor for I_DDQ Testing and Power Dissipation Measurement

Analog Integrated Circuits and Signal Processing
Online Current Testing

IEEE Design & Test
AN IDDQ SENSOR CIRCUIT FOR LOW-VOLTAGE ICS

ITC '97 Proceedings of the 1997 IEEE International Test Conference
Design and Realization of an Accurate Built-In Current Sensor Design and Realization of an Accurate Built-In Current Sensor and lddq Testing

ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Compact Built-In Current Sensor for IDDQ Testing

IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators

Journal of Electronic Testing: Theory and Applications
A Built-In Self-Test Scheme for Differential Ring Oscillators

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A simple built-in current sensor for IDDQ testing of CMOS data converters

Integration, the VLSI Journal
An indirect current sensing technique for IDDQ and IDDT tests

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A simple built-in current sensor for IDDQ testing of CMOS data converters

Integration, the VLSI Journal
Fault Coverage on RF VCOs and BIST for Wafer Sort Using Peak-to-Peak Voltage Detectors

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a practical design for built-in current sensors (BICS's) is proposed. This scheme can execute current testing during the normal circuit operation with very small impact on the performance of the circuit under test (CUT). In addition, scalable resolutions and no external voltage/current reference make this design more effective and efficient than previous designs. Moreover this scheme can be used to monitor the current-related faults of both CMOS and non-CMOS circuits. Thus it is highly suitable for design for testability (DFT) on a multiple-chip module (MCM) or to be the current monitor on the test fixture under the quality test action group (QTAG) standard.