A Gated Clock Scheme for Low Power Scan-Based BIST

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Venue:
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Year:
2001

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Cited 1

A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Abstract: In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power/energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.