Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Computers
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are presented. In this methodology, groups of scan elements are addressed in parallel and the scan-in and scan-out operations are performed separately. The compaction techniques presented reduce the number of scan-in/out operations required by skipping scan operations that do not have an affect on fault coverage. The techniques allow the number of test cycles required to be reduced by up to 45% of that achieved using regular dynamic compaction techniques alone, and by up to 98% over that achieved using a single serial scan chain methodology. In addition, the techniques are suitable for both synchronous and asynchronous circuits.