A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
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We present a method for designing test generator circuits (TCCs) that incorporate a precomputed test set TD in the patterns they produce. Our method uses width compression based on the property of d-compatibles as well as compatibles and inverse compatibles and does not require access to a gate-level model of the circuit under test. The TGC consists of a counter, which generates a set of encoded test patterns TE and a decompression circuit, which consists of simple binary decoders that generate a final sequence containing TD . We show that partially specified test sets, i.e., those that contain a large number of don't-cares, lead to more efficient TGCs. These TGCs are applicable to embedded core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results on width compression for the ISCAS'85 benchmark circuits and the full-scan versions of the ISCAS'89 benchmark circuits