Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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The trend that embedded memories will play an important role in the semiconductor market over the next few years has been widely noted. The testing of embedded memories therefore is becoming an industry-wide concern. This panel will try to clarify some important issues regarding embedded memory testing, such as the use of BIST for various testing purposes, the use of IddQ for reliability screening, the possibility of built-in redundancy analysis and self-repair, etc.