Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Optimizing error masking in BIST by output data modification
Journal of Electronic Testing: Theory and Applications
A Tool for Automatic Generation of BISTed and Transparent BISTed Rams
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Built-In Self-Testing RAM: A Practical Alternative
IEEE Design & Test
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Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper. in order to increase the effectiveness of RAM BIST. we take advantage from the regulanty of the RAM test algorithms and we show that aliasing-free signature analysis can be achieved in RAM BIST.