Test Cycle Count Reduction in a Parallel Scan BIST Environment

Authors:
Bechir Ayari;Prab Varma
Affiliations:
1315 Dell Avenue, Campbell, CA 95008, USA. bechir@hal.com;1315 Dell Avenue, Campbell, CA 95008, USA. prab@veritable.com
Venue:
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Year:
2000

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Abstract

This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based Built-In-Self-Test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of applying the vectors.