A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Time Domain Multiplexed TAM: Implementation and Comparison
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
Integration, the VLSI Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Test access is a major problem for core-based system-on-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. One of the most important issues in designing a test access architecture is testing time. Here, several issues related to the design of an optimal test access architecture with the goal of minimizing testing time are discussed. These issues include the assignment of cores to test buses, the distribution of test data width between multiple test buses, and the estimation of test data requirements to satisfy an upper bound on the testing time. Previous works [5] show that all of these problems are NP-complete. Here, we applied a Genetic Algorithm (GA) to solve these problems. Experiments were run on two hypothetical but non-trivial SOCs using the implemented GA. The results show a 40% improvement in comparison to results from [5]. The performance improvement is principally due to our removing the constraints of the necessity of serialization and allowing the system to handle serial or parallel test data loading for any core.