Pattern-based verification of connections to intellectual property cores
Integration, the VLSI Journal
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Embedded ores are being increasingly used in the design of large System-on-a-Chip(SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrator. To reduce the verification complexity, the port order fault (POF) model proposed in [1] has been used for verifying core-based designs and the corresponding verification pattern generation have been developed [2] [3]. Here we present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) proposed in [3] for SoC design verification based on POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the results of AVPG.