Zephyr: a static timing analyzer integrated in a trans-hierarchical refinement design flow

Authors:
Christophe Alexandre;Marek Sroka;Hugo Clément;Christian Masson
Affiliations:
Laboratoire LIP6, Université Paris VI, Paris, France;Laboratoire LIP6, Université Paris VI, Paris, France;Laboratoire LIP6, Université Paris VI, Paris, France;Laboratoire LIP6, Université Paris VI, Paris, France
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

The evolution of silicon technologies has fundamentally changed the physical design EDA flow, which now has to go through a progressive refinement process where interconnections evolve seamlessly from logic to final detailed routing. Furthermore the level of integration reached makes mandatory the use of hierarchical enabled design methodologies. In this paper, we present Zephyr: an Elmore Delay Static Timing Analysis engine tightly integrated in the open academic Coriolis EDA physical design platform on which tools act as algorithmic engines operating on an integrated C++ database around which they consistently interact and collaborate. Coriolis provides high level C++ and Python APIs and a unified and consistent hierarchical VLSI data model through all the design steps from logic down to final layout. We discuss here more specifically the integration issues and concepts used to support timing analysis through the progressive refinement of hierarchical designs.