On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion estimation during top-down placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel global placement with congestion control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A stochastic model to predict the routability of field-programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Techniques for area estimation of VLSI layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Congestion estimation is an important issue for design automation of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach that allows wires to have bounded-length detours to bypass congestions. The method is more realistic and precise than the previous work. The experimental results demonstrate the effectiveness of the method on routing benchmarks.