Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Data synchronized pipeline architecture: pipelining in multiprocessor environments
Journal of Parallel and Distributed Computing
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An approach to interface synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Synthesis of system-level communication by an allocation-based approach
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A codesign experiment in acoustic echo cancellation: GMDFα
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal Processors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
System-level codesign of mixed hardware-software systems
System-level codesign of mixed hardware-software systems
SIERA: a unified framework for rapid-prototyping of system-level hardware and software
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Zikimi: A Case Study in Micro Kernel Design for Multimedia Applications
Multimedia Tools and Applications
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Continuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Since their implementations generally require the use of heterogeneous resources (e.g., processor cores, ASICs) in one system with stringent design constraints, the importance of hardware/software codesign methodologies increases steadily. Interfacing heterogeneous hardware and software components together through a communication structure is particularly error prone and time consuming. Hence, on the basis of a generic architecute dedicated to telecommunication and multimedia applications, we proposed an extended communication synthesis method that provides characterization of communications and their implementation schemes in the target architecture. This method takes place after the partitioning and scheduling phase and may constitute the basis of a back-end of a codesign framework leading to HW/SW integration.