Optimal FPGA mapping and retiming with efficient initial state computation

Authors:
Jason Cong;Chang Wu
Affiliations:
Department of Computer Science, University of California, Los Angeles, CA;Department of Computer Science, University of California, Los Angeles, CA
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

For sequential circuits with given initial states, new equivalent initial states must be computed for retiming, which unfortunately is NP-hard. In this paper we propose a novel polynomial time algorithm for optimal FPGA mapping with forward retiming to minimize the clock period with guaranteed initial state computation. It enables a new methodology of separating forward retiming from backward retiming to avoid time-consuming iterations between retiming and initial state computation. Our algorithm compares very favorably with both of the conventional approaches of separate mapping followed by retiming [1, 8] and the recent approaches of combined mapping with retiming [12, 2]. It is also applicable to circuits with partial initial state assignment.