FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimal FPGA mapping and retiming with efficient initial state computation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimal clock period FPGA technology mapping for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A novel algorithm, named SeqMapII, of technology mapping with retiming for optimal clock period for K-LUT based FPGAs was recently proposed by Pan and Liu. The time complexity of their algorithm, however, is O(K^3 n^4 log (K n^2) log n) for sequential circuits with n gates, which is too high for medium and large size designs in practice. In this paper, we present three strategies to improve the performance of the approach in: 1) efficient label update with single K-cut computation based on the monotone property of labels that we showed for sequential circuits, 2) a novel approach for the K-cut computation in partial flow networks, which are much smaller in practice, 3) SCC (strongly connected component) partition to further speedup the algorithm. In practice, our algorithm works in O(K n^3 log n) time and O(Kn) space according to our experimental results. It is 2x10^4 times faster than SeqMapII-opt for computing optimal solutions and 2 times faster than SeqMapII-heu which uses very small expanded circuits as a heuristic.