A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Clock grouping: a low cost DFT methodology for delay testing
DAC '94 Proceedings of the 31st annual Design Automation Conference
Algorithm 595: An Enumerative Algorithm for Finding Hamiltonian Circuits in a Directed Graph
ACM Transactions on Mathematical Software (TOMS)
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Increasing testability by clock transformation (getting rid of those darn states)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Improving Circuit Testability by Clock Control
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
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In previous studies clock control has been inserted after design to improve the testability of a sequential circuit. In this paper we propose a two-clock control scheme that is included as a part of the logic synthesis of a finite state machine (FSM). The scheme has low area overhead and competes well with scan methods in its ability to initialize and observe circuit states. The states of the machine are assigned a pair of binary values using a novel split coding system. The purpose of the encoding is to ease navigation between any pair of states using a combination of normal and test-mode transitions. We require a Hamiltonian cycle to exist in the state transition graph. Our investigation of the FSM benchmark shows that either such a cycle already exists or can be created with the insertion of a small number of transition edges. We also present synthesis results to show that the area penalty is small.