Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Optimizing Power in ASIC Behavioral Synthesis
IEEE Design & Test
Reducing Address Bus Transitions for Low Power Memory Mapping
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Code placement in hardware/software co-synthesis to improve performance and reduce cost
Proceedings of the conference on Design, automation and test in Europe
Power optimization and management in embedded systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High-level synthesis of distributed logic-memory architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An energy-conscious algorithm for memory port allocation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Instruction code mapping for performance increase and energy reduction in embedded computer systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Off-chip memories are typically used during behavioral synthesis to store large arrays that do not fit into on-chip registers. An important power-optimization problem that arises in this context is the minimization of signal transitions on the off-chip buses connecting the ASIC and the memory. We address the problem of system power reduction through transition count minimization on the multiported memory's address buses when these arrays are accessed from memory at execution time. We exploit regularity and spatial locality in the memory accesses and determine a power-efficient mapping of behavioral array references to physical locations as well as ports of a multiport memory. Our experiments on several image processing benchmarks show significant power savings through reduced transition activity on the memory address buses, compared to a straightforward mapping scheme.