Buffer size trade-offs in input/output buffered ATM switches under various conditions
ICCCN '95 Proceedings of the 4th International Conference on Computer Communications and Networks
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
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We explore what is needed to improve and automate the process of designing a broadband ATM switch, i.e., determining the "optimal" switch parameters given hardware costs and constraints on quality of service. We present a cost model for implementation with CMOS integrated circuits, based on some prototype designs that include both input and output buffering, and combine this with a simple method for rough performance analysis to allow quick design evaluation. Experiments are presented for a range of specifications, based on an automated exhaustive search algorithm, and a framework for using nonlinear integer optimization to improve efficiency in the future is developed.