Analysis of input and output queueing for nonblocking ATM switches
IEEE/ACM Transactions on Networking (TON)
Design, analysis, and optimization of broadband ATM switches implemented in VLSI
Design, analysis, and optimization of broadband ATM switches implemented in VLSI
A predictive dynamic output buffer reconfiguration (PDOBR) architecture for ATM networks
Computer Communications
VLSI design optimization of input/output-buffered broadband ATM switches
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
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Abstract: In this paper the non-linear and complex relationship between packet loss probability and average packet delay for an input/output buffered ATM switch is studied thoroughly using our previously published analysis model. The main contribution is insight into the behavior of the switch and better understanding of the buffer size trade-offs under various traffic conditions speed-up factors, and buffer sizes. For different traffic conditions and buffer sizes, several distinct regions are identified and the behavior of the switch in those regions is explained. The results presented here can provide the basis for an optimum VLSI design methodology for input/output-buffered switches.