Lead reduction among combinatorial logic circuit

  • Authors:

  • W. V. Vilkelis

  • Affiliations:

  • IBM Data Systems Division laboratory, Poughkeepsie, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 1982

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Abstract

The paper provides a description of the behavior of lead reduction among combinatorial logic circuits. Methods by which one may design the lead reduction architecture for modular packaging schemes are developed. The methods are then applied to the design of the lead reduction architecture of an integrated circuit chip and a nine-chip cell.