Large Scale On-Chip Networks: An Accurate Multi-FPGA Emulation Platform

• Authors: Kouadri-Mostefaoui; Abdellah-Medjadji;Benaoumeur Senouci;Frederic Petrot
• Venue: DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
• Year: 2008

Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-Chip) are therefore becoming critical issues. A significant speed up of the global validation process for NoC-centric SoCs could be achieved by prototyping such systems on reconfigurable devices (FPGA). However, as SoC complexity increases with the technology scaling, existing general purpose prototyping platforms are far from being suited for large systems. In this paper we present a study for a scalable multi-FPGA platform, designed for NoCs emulation and debugging. This platform allows the integration of complete systems as well as a near cycle-accurate performance estimation.