Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Analysis of Performance Dependencies in NUCA-Based CMP Systems
SBAC-PAD '09 Proceedings of the 2009 21st International Symposium on Computer Architecture and High Performance Computing
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One of the challenges of multicore design is providing data quickly to all the processor cores running on a system. Recent proposals of hybrid and reconfigurable interconnect architectures try to take advantage of data locality to a certain extent by grouping processors that work on the same data. In this paper, we propose migrating processors instead of data to take advantage of data locality. This is realized by implementing a reconfigurable interconnect that allows reassignment of processor cores to different routers at runtime. We present the proposed architecture in detail, show a segmented hardware implementation of the proposed architecture, and discuss experimental results using PARSEC benchmark showing the performance gains of the proposed architecture. Our results show a gain in average L2 access time of up to 24% when implementing the proposed architecture compared to a hybrid architecture without reconfiguration. Finally we present area and performance data based on a detailed Verilog model and synthesis of the proposed architecture.