A measurement-based model for workload dependence of CPU errors
IEEE Transactions on Computers - The MIT Press scientific computation series
Testing for Intermittent Faults in Digital Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
IEEE Transactions on Computers
Diagnosable Systems for Intermittent Faults
IEEE Transactions on Computers
A Continuous-Parameter Markov Model and Detection Procedures for Intermittent Faults
IEEE Transactions on Computers
Error Detection Process Model, Design, and Its Impact on Computer Performance
IEEE Transactions on Computers
A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications
IEEE Transactions on Computers
Detection of Single Intermittent Faults in Sequential Circuits
IEEE Transactions on Computers
A study of intermittent faults in digital computers
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Reliability, availability, and serviceability of IBM computer systems: a quarter century of progress
IBM Journal of Research and Development
Model for transient and permanent error-detection and fault-isolation coverage
IBM Journal of Research and Development
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
A biological development model for the design of robust multiplier
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
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A great deal has been written during the past few years on the subject of diagnostic test procedures for digital systems. Almost without exception, however, the investigators have limited their interest to the detection and location of solid faults, and their test procedures are usually based on the assumption that either the fault exists for the running time of the test procedure or the time interval between the fault occurrence is less than the required time to run the test.