Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits

Authors:
Davood Shahrjerdi;Bahman Hekmatshoar;Ali Khakifirooz;Ali Afzali-Kusha
Affiliations:
Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran;Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran;Microsystems Technology Laboratories, Massachusetts Institute of Technology, 60 Vassar St. Cambridge, MA 02139, USA;Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Venue:
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Year:
2005

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Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits

Proceedings of the 14th ACM Great Lakes symposium on VLSI

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Abstract

Application of the V"T-control method is studied in ultra-thin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, V"C"N and V"C"P, are applied to the back-gates of the n- and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V"T-control method is a promising way for realizing low-power SOI logic circuits. Furthermore, the scalability of this technique is verified by extending the simulations to other generations of the ITRS roadmap.