Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits

Authors:
Davood Shahrjerdi;Bahman Hekmatshoar;Ali Afzali-Kusha;Ali Khakifirooz
Affiliations:
University of Tehran, Tehran, Iran;University of Tehran, Tehran, Iran;University of Tehran, Tehran, Iran;Massachusetts Institute of Technology, Cambridge, MA
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

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Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

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Abstract

Application of the VT-control method is studied in ultrathin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n-type and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized VT-control method is a promising way for realizing low-power SOI logic circuits.