Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design

Authors:
Qikai Chen;Saibal Mukhopadhyay;Aditya Bansal;Kaushik Roy
Affiliations:
Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN
Venue:
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Year:
2006

Citing 3
Cited 0

Fundamentals of modern VLSI devices

Fundamentals of modern VLSI devices
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Proceedings of the 40th annual Design Automation Conference
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

In this paper, we propose a general Circuit-aware Device Design methodology, which can improve the overall circuit design by taking advantages of the individual circuit characters during the device design phase. The proposed methodology analytically derives the optimal device in terms of the pre-specified circuit quality factor. We applied the proposed methodology to SRAM design and achieved significant reduction in standby leakage and access time (11% and 7%, respectively, for conventional 6T-SRAM). Also, we observed that the optimal devices selected depend considerably on the applied circuit techniques. We believe that the proposed Circuit-aware Device Design methodology will be useful in the sub-90nm technology, where different leakage components (subthreshold, gate, and junction tunneling) are comparable in magnitude. Also, in this work, we have presented a design automation framework for SRAM, which is conventionally custom designed and optimized.