Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Journal of Computational Electronics
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In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the "virtual cathode" concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed Si1驴x Ge x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS驴, a 2D device simulator from Silvaco.