Proceedings of the 40th annual Design Automation Conference
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Current status of CMOS low voltage and low power wireless IC designs
Analog Integrated Circuits and Signal Processing
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Scaling down of device sizes and supply voltage requires a commensurate scaling of transistorthreshold voltage to maintain high performance. Such scaling leads to exponential increase inleakage current, decreased noise immunity for high speed circuits, and increased defects. In thistutorial we will present design and test techniques to combat these problems in the deep sub-micronregime for bulk, SOI and future technologies. We will consider the following issues in turn:1. Device scaling and its impact on sub-threshold and gate leakage current, interconnects, andnoise immunity2. Low voltage circuit design under high intrinsic leakage, leakage monitoring and controltechniques, effective transistor stacking, multi-threshold CMOS, dynamic threshold CMOS,SOI implications. Design of low leakage data-paths and caches.3. SOI design - comparison with bulk, logic and memory design, asynchronous design4. Copper, Low k, and impact of Low k on performance5. Future technologies - Double gate fully depleted SOI, FIN FET, and 3-D SOI6. Noise modeling and analysis for high-speed precharge-evaluate circuits such as domino.Noise tolerant circuit design styles: skewed CMOS, noise tolerant domino, layout styles forhigh noise immunity7. Iddq testing of circuits with high intrinsic leakage: delta Iddq, two parameter tests. Iddwaveform analysisThis course will be useful for VLSI design engineers, managers, technologists, students, professorswho are actively involved in VLSI design or to those who need to spread their knowledge acrossmulti-disciplines. The tutorial is also intended for those who would like to know new developmentsin this field.