Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty
Proceedings of the 18th ACM Great Lakes symposium on VLSI
An expected-utility based approach to variation aware VLSI optimization under scarce information
Proceedings of the 13th international symposium on Low power electronics and design
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dominant critical gate identification for power and yield optimization in logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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The aggressive scaling of technology parameters in deep submicron (DSM) circuits has led towards an increased impact of process variations on delay and crosstalk noise. In this work, we develop a new post-layout gate sizing algorithm for simultaneous reduction of delay uncertainty and crosstalk noise under the impact of process variations. The problem of postlayout statistical gate sizing is modeled as a 2-player stochastic game and solved using Nash equilibrium theory. Due to process variations, the gate sizes are no longer deterministic, but rather behave as a probabilistic distribution over a range. Stochastic games allow the modeling of probabilistic distribution of gate size space and also effectively capture the conflicting nature of the problem. We have implemented two different strategies in which the games are ordered according to (i) the noise criticality, and (ii) the delay criticality of nets. Experimental results demonstrate the effectiveness of the developed methodology by improving both delay and crosstalk noise violations, resulting in improved yield when compared to the deterministic approach without area overhead or the need for rerouting.