Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Circuit-level techniques to control gate leakage for sub-100nm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Reducing TCAM Power Consumption and Increasing Throughput
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup
IEEE Transactions on Computers
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
DevoFlow: cost-effective flow management for high performance enterprise networks
Hotnets-IX Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks
DevoFlow: scaling flow management for high-performance networks
Proceedings of the ACM SIGCOMM 2011 conference
A high speed low power CAM with a parity bit and power-gated ML sensing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Innovative architectural and circuit techniques are reducing the dynamic power in ternary content addressable memories (TCAMs). Also, shrinking device dimensions are making transistors increasingly leaky. Due to these two trends, the static power is becoming a significant portion of the total TCAM power. This paper presents two novel ternary storage cells that exploit the unique properties of TCAMs for reducing the cell leakage. Simulation results of the proposed cells show up to 40% leakage reduction over the conventional TCAM cell at the expense of a small degradation (