A high speed low power CAM with a parity bit and power-gated ML sensing

Authors:
Anh-Tuan Do;Shoushun Chen;Zhi-Hui Kong;Kiat Seng Yeo
Affiliations:
Virtus, IC Design Centre of Excellent, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore;Virtus, IC Design Centre of Excellent, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore;Virtus, IC Design Centre of Excellent, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore;Virtus, IC Design Centre of Excellent, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

Citing 2
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A low-power ternary CAM with positive-feedback match-line sense amplifiers

IEEE Transactions on Circuits and Systems Part I: Regular Papers
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry. Thus, robust, high-speed and low-power ML sense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. Furthermore, we propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.